In recent years, research and development projects regarding nonvolatile memory devices having memory cells structured with variable resistance elements have been moved forward. A variable resistance element is an element which has a property that a resistance value reversibly changes based on electrical signals and further can store data corresponding to the resistance value in a nonvolatile manner.
Commonly known as a nonvolatile memory device including variable resistance elements is a nonvolatile memory device including memory cells, that is, so-called 1T1R memory cells each formed by connecting in series a transistor and a variable resistance element, each of which is array-arranged in a matrix at a position where a bit line intersects a word line arranged to be orthogonal to the bit line. For higher integration, also known are a nonvolatile memory device including memory cells, that is, so-called cross point 1D1R memory cells, array-arranged in a matrix, and a nonvolatile memory device including a plurality of layers of the 1D1R cross point memory cells. Each of the 1D1R cross point memory cells is formed by connecting in series a variable resistance element and a diode functioning as a current steering element, and is provided at a position where a bit line intersects a word line arranged to be orthogonal to the bit line.
PTL 1 discloses a nonvolatile memory device including 1T1R memory cells in which amorphous thin films such as rare-earth oxide films are used as variable resistance elements.
FIG. 41 is a circuit diagram of the memory cell of the nonvolatile memory device disclosed by PTL 1.
A memory cell 1001 is composed of a transistor 1002 and a variable resistance element 1003 which are electrically connected in series.
PTL 1 discloses, as a material for the variable resistance element 1003, an amorphous thin film such as a rare-earth oxide film, and discloses, as a material for an electrode, copper, silver, and zinc.
FIG. 42 is a graph showing a voltage-current change of the variable resistance element 1003 which is used in the memory cell of the nonvolatile memory device disclosed by PTL 1. At the time of writing, a potential difference is applied between V1 and V2 of FIG. 41 so that a voltage of +1.1X [V] or higher and a small amount of current are applied to the variable resistance element 1003 which thereby changes from a high resistance state to a low resistance state. At the time of erasing, a voltage having reverse polarity to that of writing is applied so that a voltage of −1.1X [V] and a current of −1.5Y [A] are applied to the variable resistance element 1003 which thereby changes from a low resistance state to a high resistance state.
PTL 1 discloses that at the time of writing, controlling the value of current upon the change of the variable resistance element 103 to the low resistance state according to a change in the on-resistance value of the transistor 1002 of FIG. 41 with its gate voltage controlled or in the like method allows a control on the resistance value of the variable resistance element 1003 in the low resistance state, and discloses applying this principle to multi-valued memories.
PTL 2 discloses a nonvolatile memory device which includes 1D1R cross point memory cells using, as a variable resistance element, a material having a perovskite type crystalline structure, and using a varistor as a bi-directional diode.
FIG. 43 schematically shows a memory cell array of a nonvolatile memory device 1200 disclosed by PTL 2. A memory cell 1280 is composed of a diode 1270 and a variable resistance element 1260 which are electrically connected in series. Numerals 1210 and 1220 denote a bit line and a word line, respectively.
In the variable resistance element 1260, a variable resistance layer 1230 of which resistance is changed by voltage application is held between an upper electrode 1240 and a lower electrode 1250.
FIG. 44 shows voltage-current characteristics of a diode 1270. As shown in FIG. 44, the diode is bi-directional and has symmetrical and non-linear voltage-current characteristics allowing a drastic increase in current at a voltage equal to or higher than a threshold voltage Vth.
PTL 2 discloses, as a material for the variable resistance layer 1230, manganese, titanium, zirconia, and a high-temperature superconducting material, manganese oxide obtained by combining the rare-earth metals such as La or Pr or a mixed crystal of La and Pr, the alkaline earth metals such as Ca or Sr or a mixed crystal of Ca and Sr, and Pr1-xCaxMnO3 (x=0.3, 0.5), and discloses, as a material for the upper electrode 1240 and the lower electrode 1250, a simple substance or alloy of Pt, Ir, Ph, and Pd, an oxide conductor such as Ir and Ru, SRO and YBCO. As a material or device for the diode, PTL 2 discloses a ZnO varistor prepared by sintering a metal oxide such as zinc oxide and a small amount of bismuth oxide, and a SrTiO3 varistor.
Furthermore, PTL 2 discloses that at the time of writing, Vpp is applied to the selected bit lines, ½ Vpp is applied to the non-selected bit line, 0 V is applied to the selected word lines, and ½ Vpp is applied to the non-selected word lines, and at the time of erasing, Vpp is applied to the selected word lines, ½ Vpp is applied to the non-selected word lines, 0 V is applied to the selected bit lines, and ½ Vpp is applied to the non-selected bit lines.
Thus, PTL 2 discloses that by using, as the diode of the 1D1R cross point memory cell, a non-linear element such as a varistor allowing the currents to flow bi-directionally, necessary currents can be flown bi-directionally at the time of writing, and moreover, optimizing the threshold voltage Vth so that the voltage ½ Vpp applied to the non-selected lines is lower than the threshold voltage Vth of the non-linear element solves the problem of current leakage to the non-selected cells, with the result that the array size of the memory cell array can be made larger and a high integration can be achieved.
[Citation List]
[Patent Literature]
[PTL 1]    Japanese Unexamined Patent Application Publication No. 2005-235360 (FIGS. 1 and 2)
[PTL 2]    Japanese Unexamined Patent Application Publication No. 2006-203098 (FIGS. 2 and 4)